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Appendix

Microcode Table

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In this part
Table 15. Control signals for each of the BF instructions.
Instr K V A S Z Cycle Control Signals
Any except 0 LD(FBI)
“.”, “,” and “?”
+ 0 0 1 INC(D) SETV(CU) LD(FA)
0 0 2 INC(IP) CLR(CC)
1 0 1 LD(D) OE(RAM)
1 0 2 INC(D) SETV(CU) LD(FA)
1 0 3 INC(IP) CLR(CC)
1 1 INC(IP) CLR(CC)
- 0 0 1 DEC(D) SETV(CU) LD(FA)
0 0 2 INC(IP) CLR(CC)
1 0 1 LD(D) OE(RAM)
1 0 2 DEC(D) SETV(CU) LD(FA)
1 0 3 INC(IP) CLR(CC)
1 1 INC(IP) CLR(CC)
< 0 0 1 DEC(DP) SETA(CU) LD(FA)
0 0 2 INC(IP) CLR(CC)
1 0 1 EN(D) WE(RAM)
1 0 2 DEC(DP) SETA(CU) LD(FA)
1 0 3 INC(IP) CLR(CC)
1 1 INC(IP) CLR(CC)
> 0 0 1 INC(DP) SETA(CU) LD(FA)
0 0 2 INC(IP) CLR(CC)
1 0 1 EN(D) WE(RAM)
1 0 2 INC(DP) SETA(CU) LD(FA)
1 0 3 INC(IP) CLR(CC)
1 1 INC(IP) CLR(CC)
[ 0 0 1 1 INC(LS)
0 0 1 2 INC(IP) CLR(CC)
0 0 0 1 INC(SP)
0 0 0 2 WE(RAM) EN(SP) EN(IP)
0 0 0 3 INC(IP) CLR(CC)
1 0 1 EN(DP) LD(D) OE(RAM) LD(FA) CLR(CC)
1 1 INC(LS)
1 2 INC(IP) CLR(CC)
] 0 0 1 1 DEC(SP)
0 0 1 2 INC(IP) CLR(CC)
0 0 0 1 EN(SP) OE(RAM) LD(IP)
0 0 0 2 INC(IP) CLR(CC)
1 0 1 EN(DP) OE(RAM) LD(D) LD(FA) CLR(CC)
1 1 DEC(LS)
1 2 INC(IP) CLR(CC)
. 0 0 0 0 LD(FBI)
0 0 0 1 SETV(CU) SETA(CU) LD(FA)
0 0 0 2 LD(FBI) CLR(CC)
0 1 0 0 LD(FBI)
0 1 0 1 SETV(CU) SETA(CU) LD(FA) LD(D) OE(RAM)
0 1 0 2 LD(FBI) CLR(CC)
1 0 0 0 LD(FBI)
1 0 0 1 SETV(CU) SETA(CU) LD(FA) EN(D) WE(RAM)
1 0 0 2 LD(FBI) CLR(CC)
0 1 1 0 0 EN(D) EN(SCR) CLR(CC)
1 1 1 0 0 LD(FA) CLR(K) INC(IP)
1 1 1 0 1 LD(FBI) CLR(CC)
1 0 LD(FBI)
1 1 INC(IP) CLR(CC)
, 0 0 0 0 LD(FBI)
0 0 0 1 SETV(CU) SETA(CU) LD(FA)
0 0 0 2 LD(FBI) CLR(CC)
0 1 0 0 LD(FBI)
0 1 0 1 SETV(CU) SETA(CU) LD(FA) LD(D) OE(RAM)
0 1 0 2 LD(FBI) CLR(CC)
1 0 0 0 LD(FBI)
1 0 0 1 SETV(CU) SETA(CU) LD(FA) EN(D) WE(RAM)
1 0 0 2 LD(FBI) CLR(CC)
0 1 1 0 0 EN(KB) CLR(CC)
1 1 1 0 0 LD(D)
1 1 1 0 1 SETV(CU) LD(FA) CLR(K) INC(IP)
1 1 1 0 2 LD(FBI) CLR(CC)
1 0 LD(FBI)
1 1 INC(IP) CLR(CC)
? 0 0 0 0 LD(FBI)
0 0 0 1 SETV(CU) SETA(CU) LD(FA)
0 0 0 2 LD(FBI) CLR(CC)
0 1 0 0 LD(FBI)
0 1 0 1 SETV(CU) SETA(CU) LD(FA) LD(D) OE(RAM)
0 1 0 2 LD(FBI) CLR(CC)
1 0 0 0 LD(FBI)
1 0 0 1 SETV(CU) SETA(CU) LD(FA) EN(D) WE(RAM)
1 0 0 2 LD(FBI) CLR(CC)
0 1 1 0 0 EN(KB) EN(OUT) CLR(CC)
1 1 1 0 0 LD(D)
1 1 1 0 1 SETV(CU) LD(FA) CLR(K) INC(IP)
1 1 1 0 2 LD(FBI) CLR(CC)
1 0 LD(FBI)
1 1 INC(IP) CLR(CC)
NOP 1 INC(IP) CLR(CC)
HLT 0 1 HLT(CLK)
0 2 INC(IP) CLR(CC)
1 1 INC(IP) CLR(CC)
INIT 0 1 CLR(CC)
1 1 1 EN(D) WE(RAM) INC(LS)
1 1 2 LD(FBI) INC(DP)
1 0 1 3 INC(IP) CLR(CC)
1 1 1 3 CLR(CC)
INIT_FINISH 1 1 CLR(DP) CLR(K) INC(IP) CLR(CC)
LOAD_SLOT 0 1 CLR(CC)
1 1 LD(D) INC(LS)
1 1 2 CLR(K) INC(IP) CLR(CC)
PROG_START 1 0 1 DEC(D)
1 1 1 DEC(LS)
1 2 INC(IP) CLR(CC)
PROG_END 0 1 END(CU) HLT(CLK)
1 1 INC(IP) CLR(CC)
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